Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory

STT-MRAM is one of the most promising non-volatile memory technologies with the potential of becoming a universal memory. However, because of its area, power and latency limitations, STT-MRAM is facing critical bottlenecks in substituting DRAM for main memory. Compared to modern DRAM technology, STT-MRAMs cell area and write power consumption are about four times larger and higher, respectively. In this paper, we study diverse device-level parameters of STT-MRAM to make the storage capacity of STT-MRAM comparable to DRAM with better performance as well as power consumption behavior. We then present analytic models to finely tune the thermal stability factor, which is related to STT-MRAM’s magnetic tunnel junction (MTJ) and the corresponding transistor, and address the challenges that storage-class STT-MRAM faces in replacing DRAM as a working memory. Our preliminary evaluation results show that, our early-stage optimized STT-MRAM can offer shorter latency and lower power consumption than a baseline DRAM by on average 18.4% and 66.2%, respectively.